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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv7170/adv7171* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 digital pal/ntsc video encoder with 10-bit ssaf? and advanced power management functional block diagram yuv to rbg matrix video timing generator 9 9 8 10 8 8 8 10 8 8 8 10 ycrcb to yuv matrix sin/cos dds block 10 10 10 10 10 10 m u l t i p l e x e r i 2 c mpu port 4:2:2 to 4:4:4 inter- polator voltage reference circuit sclock sdata alsb hsync field/ vsync blank clock gnd dac d (pin 27) dac a (pin 32) v ref r set comp 8 8 8 adv7170/adv7171 10-bit dac color data p7Cp0 p15Cp8 10-bit dac 10-bit dac real-time control circuit screset/rtc inter- polator add sync programmable luminance filter 10-bit dac dac c (pin 26) dac b (pin 31) add burst inter- polator v aa y u v power management control (sleep mode) reset programmable chrominance filter cgms & wss insertion block teletext insertion block ttxreq ttx 10 10 10 u v features itu-r bt601/656 ycrcb to pal/ntsc video encoder high quality 10-bit video dacs ssaf (super sub-alias filter) advanced power management features cgms (copy generation management system) wss (wide screen signalling) simultaneous y, u, v, c output format ntsc-m, pal-m/n, pal-b/d/g/h/i, pal-60 single 27 mhz clock required ( 3 2 oversampling) 80 db video snr 32-bit direct digital synthesizer for color subcarrier multistandard video output support: composite (cvbs) component s-video (y/c) component yuv and rgb euroscart output (rgb + cvbs/luma) component yuv + chroma video input data port supports: ccir-656 4:2:2 8-bit parallel input format 4:2:2 16-bit parallel input format smpte 170m ntsc-compatible composite video itu-r bt.470 pal-compatible composite video programmable simultaneous composite and s-video or rgb (scart)/yuv video outputs programmable luma filters (low-pass [pal/ntsc]) notch, extended (ssaf, cif and qcif) programmable chroma filters (low-pass [0.65 mhz, 1.0 mhz, 1.2 mhz and 2.0 mhz], cif and qcif) programmable vbi (vertical blanking interval) programmable subcarrier frequency and phase programmable luma delay individual on/off control of each dac ccir and square pixel operation integrated subcarrier locking to external video source color signal control/burst signal control interlaced/noninterlaced operation complete on-chip video timing generator programmable multimode master/slave operation macrovision antitaping rev 7.01 (adv7170 only)** closed captioning support teletext insertion port (pal-wst) on-board color bar generation on-board voltage reference 2-wire serial mpu interface (i 2 c ? compatible and fast i 2 c) single supply +5 v or +3.3 v operation small 44-lead pqfp/tqfp packages applications high performance dvd playback systems, portable video equipment including digital still cameras and laptop pcs, video games, pc video/multimedia and digital satellite/cable systems (set-top boxes/ird) * protected by u.s. patent numbers 5,343,196 and 5,442,355 and other intellectual property rights. ** this device is protected by u.s. patent numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. the mac rovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. please contact sales office for latest macrovision version available. note: itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). ssaf is a trademark of analog devices, inc. i 2 c is a registered trademark of philips corporation.
C2C rev. 0 adv7170/adv7171Cspecifications (v aa = +5 v 6 5% 1 , v ref = 1.235 v, r set = 150 v . all specifications t min to t max 2 unless otherwise noted.) parameter conditions 1 min typ max units static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity r set = 300 w 0.6 lsb differential nonlinearity guaranteed monotonic 1 lsb digital inputs input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in v in = 0.4 v or 2.4 v 1 m a input capacitance, c in 10 pf digital outputs output high voltage, v oh i source = 400 m a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 m a three-state output capacitance 10 pf analog outputs output current 3 r set = 150 w , r l = 37.5 w 33 34.7 37 ma output current 4 r set = 1041 w , r l = 262.5 w 5ma dac-to-dac matching 1.5 % output compliance, v oc 0 +1.4 v output impedance, r out 30 k w output capacitance, c out i out = 0 ma 30 pf voltage reference reference range, v ref i vrefout = 20 m a 1.142 1.235 1.327 v power requirements 5 v aa 4.75 5.0 5.25 v normal power mode i dac (max) 6 r set = 150 w , r l = 37.5 w 150 155 ma i dac (min) 6 r set = 1041 w , r l = 262.5 w 20 ma i cct 7 75 90 ma low power mode i dac (max) 6 80 ma i dac (min) 6 20 ma i cct 7 75 90 ma sleep mode i dac 8 0.1 m a i cct 9 0.001 m a power supply rejection ratio comp = 0.1 m f 0.01 0.5 %/% notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v. 2 temperature range t min to t max : 0 c to +70 c. 3 full drive into 37.5 w doubly terminated load. 4 minimum drive current (used with buffered/scaled output load). 5 power measurements are taken with clock frequency = 27 mhz. max t j = 110 c. 6 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 37 ma output per dac) to drive all four dacs. turning off individual dacs reduces i dac correspondingly. 7 i cct (circuit current) is the continuous current required to drive the device. 8 total dac current in sleep mode. 9 total continuous current during sleep mode. specifications subject to change without notice. 5 v specifications
C3C rev. 0 adv7170/adv7171 parameter conditions 1 min typ max units static performance 3 resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity r set = 300 w 0.6 lsb differential nonlinearity guaranteed monotonic 1 lsb digital inputs 3 input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in 3, 4 v in = 0.4 v or 2.4 v 1 m a input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 400 m a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 m a three-state output capacitance 10 pf analog outputs 3 output current 4, 5 r set = 150 w , r l = 37.5 w 33 34.7 37 ma output current 6 r set = 1041 w , r l = 262.5 w 5ma dac-to-dac matching 2.0 % output compliance, v oc 0 +1.4 v output impedance, r out 30 k w output capacitance, c out i out = 0 ma 30 pf power requirements 3, 7 v aa 3.0 3.3 3.6 v normal power mode i dac (max) 8 r set = 150 w , r l = 37.5 w 150 155 ma i dac (min) 8 r set = 1041 w , r l = 262.5 w 20 ma i cct 9 35 ma low power mode i dac (max) 8 80 ma i dac (min) 8 20 ma i cct 9 35 ma sleep mode i dac 10 0.1 m a i cct 11 0.001 m a power supply rejection ratio comp = 0.1 m f 0.01 0.5 %/% notes 1 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 1 2 temperature range t min to t max : 0 c to +70 c. 1 3 guaranteed by characterization. 1 4 full drive into 37.5 w load. 1 5 dacs can output 35 ma typically at 3.3 v (r set = 150 w and r l = 37.5 w ), optimum performance obtained at 18 ma dac current (r set = 300 w and r l = 75 w ). 1 6 minimum drive current (used with buffered/scaled output load). 1 7 power measurements are taken with clock frequency = 27 mhz. max t j = 110 c. 1 8 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 38 ma output per dac) to drive all four dacs. turning off individual dacs reduces i dac correspondingly. 1 9 i cct (circuit current) is the continuous current required to drive the device. 10 total dac current in sleep mode. 11 total continuous current during sleep mode. specifications subject to change without notice. 3.3 v specifications (v aa = +3.0 v C 3.6 v 1 , v ref = 1.235 v, r set = 150 v . all specifications t min to t max 2 unless otherwise noted.)
C4C rev. 0 adv7170/adv7171Cspecifications parameter conditions 1 min typ max units differential gain 3, 4 normal power mode 0.3 0.7 % differential phase 3, 4 normal power mode 0.4 0.7 degrees differential gain 3, 4 lower power mode 1.0 2.0 % differential phase 3, 4 lower power mode 1.0 2.0 degrees snr 3, 4 (pedestal) rms 80 db rms snr 3, 4 (pedestal) peak periodic 70 db p-p snr 3, 4 (ramp) rms 60 db rms snr 3, 4 (ramp) peak periodic 58 db p-p hue accuracy 3, 4 0.7 1.2 degrees color saturation accuracy 3, 4 0.9 1.4 % chroma nonlinear gain 3, 4 referenced to 40 ire 0.6 % chroma nonlinear phase 3, 4 0.3 0.5 degrees chroma/luma intermod 3, 4 0.2 0.4 % chroma/luma gain inequality 3, 4 1.0 1.4 % chroma/luma delay inequality 3, 4 0.5 2.0 ns luminance nonlinearity 3, 4 0.8 1.4 % chroma am noise 3, 4 82 85 db chroma pm noise 3, 4 79 81 db notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v. 2 temperature range t min to t max : 0 c to +70 c. 3 guaranteed by characterization. 4 the low pass filter only and guaranteed by design. specifications subject to change without notice. 5 v dynamic specifications (v aa = +5 v 6 5% 1 , v ref = 1.235 v, r set = 150 v . all specifications t min to t max 2 unless otherwise noted.) parameter conditions 1 min typ max units differential gain 3 normal power mode 1.0 % differential phase 3 normal power mode 0.5 degrees differential gain 3 lower power mode 0.6 % differential phase 3 lower power mode 0.5 degrees snr 3 (pedestal) rms 78 db rms snr 3 (pedestal) peak periodic 70 db p-p snr 3 (ramp) rms 60 db rms snr 3 (ramp) peak periodic 58 db p-p hue accuracy 3 1.0 degrees color saturation accuracy 3 1.0 % luminance nonlinearity 3, 4 1.4 % chroma am noise 3, 4 80 db chroma pm noise 3, 4 79 db chroma nonlinear gain 3, 4 referenced to 40 ire 0.6 % chroma nonlinear phase 3, 4 0.3 0.5 degrees chroma/luma intermod 3, 4 0.2 0.4 % notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v. 2 temperature range t min to t max : 0 c to +70 c. 3 guaranteed by characterization. 4 these specifications are for the low-pass filter only and guaranteed by design. for other internal filters, see figure 4. specifications subject to change without notice. 3.3 v dynamic specifications (v aa = +3.0 v C 3.6 v 1 , v ref = 1.235 v, r set = 150 v . all specifications t min to t max 2 unless otherwise noted.)
adv7170/adv7171 C5C rev. 0 5 v timing specifications (v aa = 4.75 v C 5.25 v 1 , v ref = 1.235 v, r set = 150 v . all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max units mpu port 3, 4 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 m s sclock low pulsewidth, t 2 1.3 m s hold time (start condition), t 3 after this period the first clock is generated 0.6 m s setup time (start condition), t 4 relevant for repeated start condition 0.6 m s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 m s analog outputs 3, 5 analog output delay 7ns dac analog output skew 0 ns clock control and pixel port 5, 6 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 3.5 ns data hold time, t 12 4ns control setup time, t 11 4ns control hold time, t 12 3ns digital output access time, t 13 11 16 ns digital output hold time, t 14 4 8ns pipeline delay, t 15 4 48 clock cycles teletext 3, 4, 7 digital output access time, t 16 20 ns data setup time, t 17 2ns data hold time, t 18 6ns reset control 3, 4 reset low time 6 ns notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v range. 2 temperature range t min to t max : 0 o c to +70 o c. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p15Cp0 pixel controls: hsync , field/ vsync , blank clock input: clock 7 teletext port consists of the following: teletext output: ttxreq teletext input: ttx specifications subject to change without notice.
C6C rev. 0 adv7170/adv7171Cspecifications 3.3 v timing specifications (v aa = 3.0 v C 3.6 v 1 , v ref = 1.235 v, r set = 150 v . all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max units mpu port 3, 4 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 m s sclock low pulsewidth, t 2 1.3 m s hold time (start condition), t 3 after this period the first clock is generated 0.6 m s setup time (start condition), t 4 relevant for repeated start condition 0.6 m s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 m s analog outputs 3, 5 analog output delay 7ns dac analog output skew 0 ns clock control and pixel port 4, 5, 6 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 3.5 ns data hold time, t 12 4ns control setup time, t 11 4ns control hold time, t 12 3ns digital output access time, t 13 12 ns digital output hold time, t 14 8ns pipeline delay, t 15 48 clock cycles teletext 3, 4, 7 digital output access time, t 16 23 ns data setup time, t 17 2ns data hold time, t 18 6ns reset control 3, 4 reset low time 6 ns notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v range. 2 temperature range t min to t max : 0 o c to +70 o c. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p15Cp0 pixel controls: hsync , field/ vsync , blank clock input: clock 7 teletext port consists of the following: teletext output: ttxreq teletext input: ttx specifications subject to change without notice.
adv7170/adv7171 C7C rev. 0 t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sdata sclock figure 1. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync , field/ vsync , blank cb y cr y cb y hsync , field/ vsync , blank t 13 t 14 control i/ps control o/ps figure 2. pixel and control data timing diagram t 16 t 17 t 18 4 clock cycles 4 clock cycles 4 clock cycles 3 clock cycles 4 clock cycles txtreq clock txt figure 3. teletext timing diagram
adv7170/adv7171 C8C rev. 0 absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital input pin . gnd C 0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +260 c analog outputs to gnd 2 . . . . . . . . . . . gnd C 0.5 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. package thermal performance the 44-pqfp package used for this device takes advantage of an adi patented thermal coastline lead frame construction. this maximizes heat transfer into the leads and reduces the package thermal resistance. the junction-to-ambient ( q ja ) thermal resistance in still air on a four-layer pcb is 35.5 c/w. the junction-to-case thermal resis- tance ( q jc ) is 13.75 c/w. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7170/adv7171 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, pr oper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configurations 12 13 14 15 16 17 18 19 20 21 22 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 pin 1 identifier adv7170/adv7171 pqfp/tqfp top view (not to scale) 29 30 31 32 27 28 25 26 23 24 33 v ref dac a dac b v aa gnd v aa dac d blank p13 p14 p15 hsync field/ vsync alsb v aa p5 p6 p7 p8 p9 p10 p11 p12 gnd v aa dac c comp sdata sclock gnd v aa gnd reset clock gnd p4 p3 p2 p1 p0 ttx ttxreq r set screset/ rtc warning! esd sensitive device ordering guide temperature package package model range descriptions options adv7170ks 0 c to +70 c plastic quad flatpack s-44 adv7170su 0 c to +70 c thin plastic quad flatpack su-44 adv7171ks 0 c to +70 c plastic quad flatpack s-44 ADV7171SU 0 c to +70 c thin plastic quad flatpack su-44 table i. allowable operating conditions for ks and su package options ks su conditions 3 v 5 v 3 v 5 v 4 dac on double 75r 1 yes yes yes no 4 dac on low power 2 yes yes yes no 4 dac on buffering 3 yes yes yes yes 3 dac on double 75r yes yes yes no 3 dac on low power yes yes yes yes 3 dac on buffering yes yes yes yes 2 dac on double 75r yes yes yes yes 2 dac on low power yes yes yes yes 4 dac on buffering yes yes yes yes notes 1 dac on double 75r refers to a condition where the dacs are terminated in a double 75r load and low power mode is disabled. 2 dac on low power refers to a condition where the dacs are terminated in a double 75r load and low power mode is enabled. 3 dac on buffering refers to a condition where the dac current is reduced to 5 ma and external buffers are used to drive the video load.
adv7170/adv7171 C9C rev. 0 pin function descriptions input/ mnemonic output function p15Cp0 i 8-bit 4:2:2 multiplexed ycrcb pixel port (p7Cp0) or 16-bit ycrcb pixel port (p15Cp0). p0 represents the lsb. clock i ttl clock input. requires a stable 27 mhz reference clock for standard operation. alter- natively, a 24.52 mhz (ntsc) or 29.5 mhz (pal) can be used for square pixel operation. hsync i/o hsync (modes 1 and 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) sync signals. field/ vsync i/o dual function field (mode 1) and vsync (mode 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) these control signals. blank i/o video blanking control signal. the pixel inputs are ignored when this is logic level 0. this signal is optional. screset/rtc i this pin can be configured as an input by setting mr22 and mr21 of mode register 2. it can be configured as a subcarrier reset pin, in which case a high-to-low transition on this pin will reset the subcarrier to field 0. alternatively, it may be configured as a real-time control (rtc) input. v ref i/o voltage reference input for dacs or voltage reference output (1.235 v). r set i a 150 w resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals. comp o compensation pin. connect a 0.1 m f capacitor from comp to v aa . for optimum dynamic performance in low power mode, the value of the comp capacitor can be lowered to as low as 2.2 nf. dac a o pal/ntsc composite video output. full-scale output is 180 ire (1286 mv) for ntsc and 1300 mv for pal. dac c o red/s-video c/v analog output. dac d o green/s-video y/y analog output dac b o blue/composite/u analog output. sclock i mpu port serial interface clock input. sdata i/o mpu port serial data input/output. alsb i ttl address input. this signal set up the lsb of the mpu address. reset i the input resets the on chip timing generator and sets the adv7170/adv7171 into default mode. this is ntsc operation, timing slave mode 0, 8 bit operation, 2 composite and s video out and dac b powered on and dac d powered off. ttx/v aa i teletext data/defaults to v aa when teletext not selected (enables backward compatibility to adv7175/adv7176). ttxreq/gnd o teletext data request signal/ defaults to gnd when teletext not selected (enables back- ward compatibility to adv7175/adv7176). v aa p power supply (+3 v to +5 v). gnd g ground pin.
adv7170/adv7171 C10C rev. 0 general description the adv7170/adv7171 is an integrated digital video encoder that converts digital ccir-601 4:2:2 8 or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. the on-board ssaf (super sub-alias filter) with extended luminance frequency response and sharp stopband attenuation, enables studio quality video playback on modern tvs, giving optimal horizontal line resolution. an advanced power management circuit enables optimal control of power consumption in both normal operating modes and power-down or sleep modes. the adv7170/adv7171 also supports both pal and ntsc square pixel operation. the parts also incorporate wss and cgms-a data control generation. the output video frames are synchronized with the incoming data timing reference codes. optionally, the encoder accepts (and can generate) hsync , vsync and field timing sig- nals. these timing signals can be adjusted to change pulsewidth and position while the part is in the master mode. the encoder requires a single two times pixel rate (27 mhz) clock for stan- dard operation. alternatively, the encoder requires a 24.54 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode operation. all internal timing is generated on-chip. a separate teletext port enables the user to directly input tele- text data during the vertical blanking interval. the adv7170/ad v7171 modes are set up over a t wo-wire serial bidirectional port (i 2 c compatible) with two slave addresses. functionally, the adv7171 and adv7170 are the same with the exception that the adv7170 can output the macrovision anticopy algorithm. the adv7170/adv7171 is packaged in a 44-lead pqfp pack- age and a 44-lead tqfp package. data path description for pal b, d, g, h, i, m, n and ntsc m, n modes, ycrcb 4:2:2 data is input via the ccir-656 compatible pixel port at a 27 mhz data rate. the pixel data is demultiplexed to form three data paths. y typically has a range of 16 to 235, cr and cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both y, cb and cr. the adv7170/ adv7171 supports pal (b, d, g, h, i, m, n) and ntsc (with and without pedestal) standards. the appropriate sync, blank and burst levels are added to the ycrcb data. macrovision antitaping (adv7170 only), closed-captioning and teletext levels are also added to y and the resultant data is interpolated to a rate of 27 mhz. the interpolated data is filtered and scaled by three digital fir filters. the u and v signals are modulated by the appropriate sub- carrier sine/cosine phases and added together to make up the chrominance signal. the luma (y) signal can be delayed 1C3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. the luma and chroma signals are then added together to make up the composite video signal. all edges are slew rate limited. the ycrcb data is also used to gen erate rgb data with ap- propriate sync and blank levels. the rgb data is in synchronization with the composite video output. alternatively, analog yuv data can be generated instead of rgb. the four l0-bit dacs can be used to output: 1. composite video + rgb video. 2. composite video + yuv video. 3. two composite video signals + luma and chroma (y/c) signals. alternatively, each dac can be individually powered off if not required. video output levels are illustrated in appendix 6. internal filter response the y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (ssaf) response, a cif response and a qcif re- sponse. the uv filter supports several different frequency re- sponses, including four low-pass responses, a cif response and a qcif response, these can be seen in the following figures 4 to 18. filter type filter selection passband ripple (db) 3 db bandwidth (mhz) stopband cutoff (mhz) stopband attenuation (db) mr04 0 0 0 0 1 1 1 mr03 0 0 1 1 0 0 1 mr02 0 1 0 1 0 1 0 low pass (ntsc) low pass (pal) notch (ntsc) notch (pal) extended (ssaf) cif qcif 0.091 0.15 0.015 0.095 0.051 0.018 monotonic 4.157 4.74 6.54 6.24 6.217 3.0 1.5 7.37 7.96 8.3 8.0 8.0 7.06 7.15 C56 C64 C68 C66 C61 C61 C50 figure 4. luminance internal filter specifications filter type filter selection passband ripple (db) 3 db bandwidth (mhz) stopband cutoff (mhz) stopband attenuation (db) mr07 0 0 0 0 1 1 1 mr06 0 0 1 1 0 0 1 mr05 0 1 0 1 0 1 0 1.3 mhz low pass 0.65 mhz low pass 1.0 mhz low pass 2.0 mhz low pass reserved cif qcif 0.084 monotonic monotonic 0.0645 0.084 monotonic 1.395 0.65 1.0 2.2 0.7 0.5 3.01 3.64 3.73 5.0 3.01 4.08 C45 C58.5 C49 C40 C45 C50 figure 5. chrominance internal filter specifications
adv7170/adv7171 C11C rev. 0 frequency C mhz 0 C70 0 2 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 6. ntsc low-pass luma filter frequency C mhz 0 C70 0 2 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 7. pal low-pass luma filter frequency C mhz 0 C70 0 2 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 8. ntsc notch luma filter frequency C mhz 0 C70 0 2 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 9. pal notch luma filter frequency C mhz 0 C70 02 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 10. extended mode (ssaf) luma filter frequency C mhz 0 C70 02 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 11. cif luma filter
adv7170/adv7171 C12C rev. 0 frequency C mhz 0 C70 02 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 12. qcif luma filter frequency C mhz 0 C70 02 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 13. 1.3 mhz low-pass chroma filter frequency C mhz 0 C70 02 magnitude C db 46 81012 C10 C30 C40 C50 C60 C20 figure 14. 0.65 mhz low-pass chroma filter frequency C mhz 0 C70 02 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 15. 1.0 mhz low-pass chroma filter frequency C mhz 0 C70 02 magnitude C db 46 81012 C10 C30 C40 C50 C60 C20 figure 16. 2.0 mhz low-pass chroma filter frequency C mhz 0 C70 02 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 17. cif chroma filter
adv7170/adv7171 C13C rev. 0 color bar generation the adv7170/adv7171 can be configured to generate 75% amplitude, 75% saturation (75/7.5/75/7.5) for ntsc or 75% amplitude, 100% saturation (100/0/75/0) for pal color bars. these are enabled by setting mr17 of mode register 1 to logic 1. square pixel mode the adv7170/adv7171 can be used to operate in square pixel mode. for ntsc operation, an input clock of 24.5454 mhz is required. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accord- ingly for square pixel mode operation . color signal control the color information can be switched on and off the video output using bit mr24 of mode register 2. burst signal control the burst information can be switched on and off the video output using bit mr25 of mode register 2. ntsc pedestal control the pedestal on both odd and even fields can be controlled on a line-by-line basis using the ntsc pedestal control registers. this allows the pedestals to be controlled during the vertical blanking interval (lines 10 to 25 and lines 273 to 288). pixel timing description the adv7170/adv7171 can operate in either 8-bit or 16-bit ycrcb mode. 8-bit ycrcb mode this default mode accepts multiplexed ycrcb inputs through the p7-p0 pixel inputs. the inputs follow the sequence cb0, y0 cr0, y1 cb1, y2, etc. the y, cb and cr data are input on a rising clock edge. 16-bit ycrcb mode this mode accepts y inputs through the p7Cp0 pixel inputs and multiplexed crcb inputs through the p15Cp8 pixel inputs. the data is loaded on every second rising edge of clock. the inputs follow the sequence cb0, y0 cr0, y1 cb1, y2, etc. subcarrier reset together with the screset/rtc pin, and bits mr22 and mr21 of mode register 2, the adv7170/adv7171 can be used in subcarrier reset mode. the subcarrier will reset to field 0 at the start of the following field when a low-to-high transition occurs on this input pin. real-time control together with the screset/rtc pin, and bits mr22 and mr21 of mode register 2, the adv7170/adv7171 can be used to lock to an external video source. the real-time control mode allows the adv7170/adv7171 to automatically alter the subcarrier frequency to compensate for line length variation. when the part is connected to a device that outputs a digital datastream in the rtc format (such as a adv7185 video de- coder, see figure 19), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. this digital datastream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is 2 clock cycles long. 00hex should be written into all four subcarrier frequency registers when using this mode. video timing description the adv7170/adv7171 is intended to interface to off- the-shelf mpeg1 and mpeg2 decoders. consequently, the adv7170/adv7171 accepts 4:2:2 ycrcb pixel data via a ccir-656 pixel port and has several video timing modes of operation that allow it to be configured as either system master video timing generator or a slave to the system video timing generator. the adv7170/adv7171 generates all of the re- quired horizontal and vertical timing periods and levels for the analog video outputs. the adv7170/adv7171 calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. in addition, the adv7170/adv7171 supports a pal or ntsc square pixel operation in slave mode. the part requires an input pixel clock of 24.5454 mhz for ntsc and an input pixel clock of 29.5 mhz for pal. the internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. the adv7170/adv7171 has four distinct master and four distinct slave timing configurations. timing control is estab- lished with the bidirectional sync , blank and field/ vsync pins. timing mode register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. frequency C mhz 0 C70 02 magnitude C db 4681012 C10 C30 C40 C50 C60 C20 figure 18. qcif chroma filter
adv7170/adv7171 C14C rev. 0 composite video e.g., vcr or cable m u x hsync field/ vsync clock green/luma/y red/chroma/v blue/composite/u composite adv7170/adv7171 p7Cp0 screset/rtc mpeg decoder video decoder (e.g., adv7185) h/ltransition count start low 128 rtc time slot: 01 14 67 68 not used in adv7175a/adv7176a 19 valid sample invalid sample fscpll increment 1 8/llc 5 bits reserved sequence bit 2 reset bit 3 reserved 4 bits reserved 21 0 13 14 bits reserved notes: 1 f sc pll increment is 22 bits long, value loaded into adv7175a/adv7176a fsc dds register is f sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the adv7170/adv7171. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset adv7175a/adv7176as dds 0 figure 19. rtc timing and connections vertical blanking data insertion it is possible to allow encoding of incoming ycbcr data on those lines of vbi that do not bear line sync or pre-/post-equalizat ion pulses (see figures 21 to 32). this mode of operation is called partial blanking and is selected by setting mr31 to 1. it all ows the insertion of any vbi data (opened vbi) into the encoded output waveform. this data is present in digitized incoming ycbcr data stream (e.g., wss data, cgms, vps, etc.). alternatively, the entire vbi may be blanked (no vbi data inserted) on these lines by setting mr31 to 0. the complete vbi is comprised of the following lines: 525/60 systems, lines 525 to 21 for field 1 and lines 262 to line 284 for field 2. 625/50 systems, lines 624 to line 22 and lines 311 to 335. the opened vbi consists of: 525/60 systems, lines 10 to 21 for field 1 and second half of line 273 to line 284 for field 2. 625/50 systems, line 7 to line 22 and lines 319 to 335. mode 0 (ccir-656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the adv7170/adv7171 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately bef ore and after each line during active picture and retrace. mode 0 is illustrated in figure 20. the hsync , field/ vsync and blank (if not used) pins should be tied high during this mode.
adv7170/adv7171 C15C rev. 0 y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 llnes/60hz) pal system (625 lines/50hz) y figure 20. timing mode 0 (slave mode) mode 0 (ccir-656): master option (timing register 0 tr0 = x x x x x 0 0 1) the adv7170/adv7171 generates h, v and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir656 standard. the h bit is output on the hsync pin, the v bit is output on the blank pin and the f bit is output on the field/ vsync pin. mode 0 is illustrated in figure 21 (ntsc) and figure 22 (pal). the h, v and f transitions relative to the video waveform are illustrated in figure 23. 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f figure 21. timing mode 0 (ntsc master mode)
adv7170/adv7171 C16C rev. 0 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 figure 22. timing mode 0 (pal master mode) analog video h f v figure 23. timing mode 0 data transitions (master mode)
adv7170/adv7171 C17C rev. 0 mode 1: slave option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 0) in this mode the adv7170/adv7171 accepts horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is dis- abled, the adv7170/adv7171 automatically blanks all normally blank lines as per ccir-624. mode 1 is illustrated in figure 24 (ntsc) and figure 25 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank field figure 24. timing mode 1 (ntsc) 622 623 624 625 1 2 3 4 5 67 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank field display 320 figure 25. timing mode 1 (pal)
adv7170/adv7171 C18C rev. 0 mode 1: master option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 1) in this mode the adv7170/adv7171 can generate horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blanks all normally blank lines as per ccir-624. pixel data is latched on the risin g clock edge following the timing signal transitions. mode 1 is illustrated in figure 24 (ntsc) and figure 25 (pal). figure 26 i llus- trates the hsync , blank and field for an odd or even field transition relative to the pixel data. field pixel data pal = 12 * clock/2 ntsc = 16 * clock/2 pal = 132 * clock/2 ntsc = 122 * clock/2 cb y cr y hsync blank figure 26. timing mode 1 odd/even field transitions master/slave mode 2: slave option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 0) in this mode the adv7170/adv7171 accepts horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 27 (ntsc) and figure 28 (pal). 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank vsync figure 27. timing mode 2 (ntsc)
adv7170/adv7171 C19C rev. 0 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank display 320 vsync figure 28. timing mode 2 (pal) mode 2: master option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 1) in this mode the adv7170/adv7171 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 27 (ntsc) and figure 28 (pal). figure 29 illus- trates the hsync , blank and vsync for an even-to-odd field transition relative to the pixel data. figure 30 illustrates the hsync , blank and vsync for an odd-to-even field transition relative to the pixel data. pal = 12 * clock/2 ntsc = 16 * clock/2 hsync vsync blank pixel data pal = 132 * clock/2 ntsc = 122 * clock/2 cb y cr y figure 29. timing mode 2 even-to-odd field transition master/slave pal = 864 * clock/2 ntsc = 858 * clock/2 pal = 132 * clock/2 ntsc = 122 * clock/2 hsync vsync blank pixel data pal = 12 * clock/2 ntsc = 16 * clock/2 cb y cr y cb figure 30. timing mode 2 odd-to-even field transition master/slave
adv7170/adv7171 C20C rev. 0 mode 3: master/slave option hsync , blank , field (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode the adv7170/adv7171 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync is high indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blanks all normally blank lines as per ccir-624. mode 3 is illustrated in figure 31 (ntsc) and figure 32 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank field figure 31. timing mode 3 (ntsc) 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank field display 320 figure 32. timing mode 3 (pal)
adv7170/adv7171 C21C rev. 0 output video timing the video timing generator generates the appropriate sync, blank and burst sequence that controls the output analog waveforms. these sequences are summarized below. in slave modes, the following sequences are synchronized with the input timing control signals. in master modes, the timing generator free runs and generates the following sequences in addition to the output timing control signals. ntscCinterlaced: scan lines 1C9 and 264C272 are always blanked and vertical sync pulses are included. scan lines 10C 21, 525, and 262, 263, 273C284 are also blanked and can be used for closed captioning data. burst is disabled on lines 1C6, 261C269 and 523C525. ntscCnoninterlaced: scan lines 1C9 are always blanked, and vertical sync pulses are included. scan lines 10C21 are also blanked and can be used for closed captioning data. burst is disabled on lines 1C6, 261C262. palCinterlaced: scan lines 1C6, 311C318 and 624C625 are always blanked, and vertical sync pulses are included in fields 1, 2, 5 and 6. scan lines 1C5, 311C319 and 624C625 are al- ways blanked, and vertical sync pulses are included in fields 3, 4, 7 and 8. the remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. burst is disabled on lines 1C6, 311C318 and 623C625 in fields 1, 2, 5 and 6. burst is disabled on lines 1C5, 311C319 and 623C625 in fields 3, 4, 7 and 8. palCnoninterlaced: scan lines 1C6 and 311C312 are always blanked, and vertical sync pulses are included. the remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. burst is disabled on lines 1C5, 310C312. power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset pin. this initializes the pixel port so that the pixel inputs, p7Cp0 are selected. after reset, the adv7170/ adv7171 is automatically set up to operate in ntsc mode. subcarrier frequency code 21f07c16hex is loaded into the subcarrier frequency registers. all other registers, with the exception of mode register 0, are set to 00h. all bits in mode register 0 are set to logic level 0 except bit mr44. bit mr44 of mode register 4 is set to logic 1. this enables the 7.5 ire pedestal. sch phase mode the sch phase is configured in default mode to reset every four (ntsc) or eight (pal) fields to avoid an accumulation of sch phase error over time. in an ideal system, zero sch phase error would be maintained forever, but in reality, this is impos- sible to achieve due to clock frequency variations. this effect is reduced by the use of a 32-bit dds, which generates this sch. resetting the sch phase every four or eight fields avoids the accumulation of sch phase error, and results in very minor sch phase jumps at the start of the four or eight field sequence. resetting the sch phase should not be done if the video source does not have stable timing or the adv7170/adv7171 is con- figured in rtc mode (mr21 = 1 and mr22 = 1). under these conditions (unstable video) the subcarrier phase reset should be enabled (mr22 = 0 and mr21 = 1) but no reset ap plied. in this configuration the sch phase will never be reset, which means that the output video will now track the unstable input video. the subcarrier phase reset, when applied, will reset the sch phase to field 0 at the start of the next field (e.g., subcarrier phase reset applied in field 5 [pal] on the start of the next field sch phase will be reset to field 0). mpu port description the adv7170 and adv7171 support a two-wire serial (i 2 c compatible) microprocessor bus driving multiple peripherals. two inputs, serial data (sdata) and serial clock (sclock), carry information between any device connected to the bus. each slave device is recognized by a unique address. the adv7170 and adv7171 each have four possible slave ad- dresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 33 and figure 34. the lsb sets either a read or write operation. logic level 1 corresponds to a read operation, while logic level 0 corresponds to a write operation. a 1 is set by setting the alsb pin of the adv7170/adv7171 to logic level 0 or logic level 1. 1 x 10101a1 address control set up by alsb read/write control 0 write 1 read figure 33. adv7170 slave address 0 x 10 1 01a1 address control set up by alsb read/write control 0 write 1 read figure 34. adv7171 slave address to control the various devices on the bus, the following proto- col must be followed: first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sdata while sclock remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits transfer from msb down to lsb. the pe- ripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sdata and sclock lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master will write information to the peripheral. a logic 1 on the lsb of the first byte means that the master will read informa- tion from the peripheral.
adv7170/adv7171 C22C rev. 0 the adv7170/adv7171 acts as a standard slave device on the bus. the data on the sdata pin is 8 bits long, supporting the 7-bit addresses, plus the r/ w bit. the adv7170 has 48 subaddresses and the adv7171 has 26 subaddresses to enable access to the internal registers. it therefore interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto increment allows data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique sub address register on a one-by-one basis without having to update all the registers. there is one excep- tion. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the auto increment function should then be used to increment and access subcarrier frequency registers 1, 2 and 3. the subcarrier frequency registers should not be accessed independently. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sclock high pe- riod, the user should issue only one start condition, one stop condition or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adv7170/adv7171 will not issue an acknowledge and will return to the idle condition. if, in auto-increment mode the user exceeds the highest subaddress, the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be output until the master device issues a no- acknowledge. this indicates the end of a read. a no- acknowledge condition is where the sdata line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the adv7170/adv7171 and the part will re- turn to the idle condition. 1-7 8 9 1-7 8 9 1-7 8 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock figure 35. bus data transfer figure 35 illustrates an example of data transfer for a read se- quence and the start and stop conditions. figure 36 shows bus write and read sequences. register accesses the mpu can write to or read from all of the adv7170/ adv7171 registers except the subaddress register, which is a write-only register. the subaddress register determines which register the next read or write operation accesses. all communi- cations with the part through the bus start with an access to the subaddress register. a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the following section describes each register, including subaddress register, mode registers, subcarrier freque ncy registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers and ntsc pedestal control registers, in terms of its configuration. subaddress register (sr7Csr0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus, and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 37 shows the various operations under the control of the subaddress register. zero should always be written to sr7Csr6. register select (sr5Csr0) these bits are set up to point to the required starting address. mode register 0 mr0 (mr07Cmr00) (address [sr4Csr0] = 00h) figure 38 shows the various operations under the control of mode register 0. this register can be read from as well as written to. mr0 bit description encode mode control (mr01Cmr00) these bits are used to set up the encode mode. the adv7170/ adv7171 can be set up to output ntsc, pal (b, d, g, h, i) and pal (m, n) standard video. luminance filter control (mr02Cmr04) these bits specify which luma filter is to be selected. the filter selection is made independent of whether pal or ntsc is selected. chrominance filter control (mr05Cmr07) these bits select the chrominance filter. a low-pass filter can be selected with a choice of cutoff frequencies, 0.65 mhz, 1.0 mhz, 1.3 mhz or 2 mhz, along with a choice of cif or qcif filters. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a (s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m ) data p write sequence read sequence a (s) = no-acknowledge by slave a (m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit figure 36. write and read sequences
adv7170/adv7171 C23C rev. 0 sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 zero should be written to these bits sr7Csr5 (000) sr5 sr4 sr3 sr2 sr1 sr0 0 0 0 0 0 0 mode register 0 0 0 0 0 0 1 mode register 1 0 0 0 0 1 0 mode register 2 0 0 0 0 1 1 mode register 3 0 0 0 1 0 0 mode register 4 0 0 0 1 0 1 reserved 0 0 0 1 1 0 reserved 0 0 0 1 1 1 timing mode register 0 0 0 1 0 0 0 timing mode register 1 0 0 1 0 0 1 subcarrier frequency register 0 0 0 1 0 1 0 subcarrier frequency register 1 0 0 1 0 1 1 subcarrier frequency register 2 0 0 1 1 0 0 subcarrier frequency register 3 0 0 1 1 0 1 subcarrier phase register 0 0 1 1 1 0 closed captioning extended data-byte 0 0 0 1 1 1 1 closed captioning extended data-byte 1 0 1 0 0 0 0 closed captioning data-byte 0 0 1 0 0 0 1 closed captioning data-byte 1 0 1 0 0 1 0 ntsc pedestal control reg 0 0 1 0 0 1 1 ntsc pedestal control reg 1 0 1 0 1 0 0 ntsc pedestal control reg 2 0 1 0 1 0 1 ntsc pedestal control reg 3 0 1 0 1 1 0 cgms_wss_0 0 1 0 1 1 1 cgms_wss_1 0 1 1 0 0 0 cgms_wss_2 0 1 1 0 0 1 teletext request position adv7171 subaddress register sr5 sr4 sr3 sr2 sr1 sr0 adv7170 subaddress register 0 0 0 0 0 0 mode register 0 0 0 0 0 0 1 mode register 1 0 0 0 0 1 0 mode register 2 0 0 0 0 1 1 mode register 3 0 0 0 1 0 0 mode register 4 0 0 0 1 0 1 reserved 0 0 0 1 1 0 reserved 0 0 0 1 1 1 timing mode register 0 0 0 1 0 0 0 timing mode register 1 0 0 1 0 0 1 subcarrier frequency register 0 0 0 1 0 1 0 subcarrier frequency register 1 0 0 1 0 1 1 subcarrier frequency register 2 0 0 1 1 0 0 subcarrier frequency register 3 0 0 1 1 0 1 subcarrier phase register 0 0 1 1 1 0 closed captioning extended data-byte 0 0 0 1 1 1 1 closed captioning extended data-byte 1 0 1 0 0 0 0 closed captioning data-byte 0 0 1 0 0 0 1 closed captioning data-byte 1 0 1 0 0 1 0 ntsc pedestal control reg 0 0 1 0 0 1 1 ntsc pedestal control reg 1 0 1 0 1 0 0 ntsc pedestal control reg 2 0 1 0 1 0 1 ntsc pedestal control reg 3 0 1 0 1 1 0 cgms_wss_0 0 1 0 1 1 1 cgms_wss_1 0 1 1 0 0 0 cgms_wss_2 0 1 1 0 0 1 teletext request position 0 1 1 0 1 0 reserved 0 1 1 0 1 1 reserved 0 1 1 1 0 0 reserved 0 1 1 1 0 1 reserved 0 1 1 1 1 0 macrovision registers 0 1 1 1 1 1 macrovision registers 1 0 0 0 0 0 macrovision registers 1 0 0 0 0 1 macrovision registers 1 0 0 0 1 0 macrovision registers 1 0 0 0 1 1 macrovision registers 1 0 0 1 0 0 macrovision registers 1 0 0 1 0 1 macrovision registers 1 0 0 1 1 0 macrovision registers 1 0 0 1 1 1 macrovision registers 1 0 1 0 0 0 macrovision registers 1 0 1 0 0 1 macrovision registers 1 0 1 0 1 0 macrovision registers 1 0 1 0 1 1 macrovision registers 1 0 1 1 0 0 macrovision registers 1 0 1 1 0 1 macrovision registers 1 0 1 1 1 0 macrovision registers 1 0 1 1 1 1 macrovision registers figure 37. subaddress register map chroma filter select mr07 mr06 0 0 0 1.3 mhz low pass filter mr05 0 0 1 0.65 mhz low pass filter 0 1 0 1.0 mhz low pass filter 0 1 1 2.0 mhz low pass filter 1 0 0 reserved 1 0 1 cif 1 1 0 q cif 1 1 1 reserved mr01 mr00 mr07 mr02 mr03 mr05 mr06 mr04 output video standard selection mr01 mr00 0 0 ntsc 0 1 pal (b, d, g, h, i) 1 0 pal (m) 1 1 reserved luma filter select mr04 mr03 0 0 0 low pass filter (ntsc) mr02 0 0 1 low pass filter (pal) 0 1 0 notch filter (ntsc) 0 0 1 notch filter (pal) 1 0 0 extended mode 1 0 1 cif 1 1 0 q cif 1 1 1 reserved figure 38. mode register 0
adv7170/adv7171 C24C rev. 0 mode register 1 mr1 (mr17Cmr10) (address (sr4Csr0) = 01h) figure 39 shows the various operations under the control of mode register 1. this register can be read from as well as written to. mr1 bit description interlaced mode control (mr10) this bit is used to set up the output to interlaced or noninter- laced mode. this mode is only relevant when the part is in composite video mode. closed captioning field control (mr12Cmr11) these bits control the fields on which closed captioning data is displayed; closed captioning information can be displayed on an odd field, even field or both fields. dac control (mr16Cmr13) these bits can be used to power down the dacs. this can be used to reduce the power consumption of the adv7170/ adv7171 if any of the dacs are not required in the application. color bar control (mr17) this bit can be used to generate and output an internal color bar test pattern. the color bar configuration is 75/7.5/75/7.5 for ntsc and 100/0/75/0 for pal. it is important to note that when color bars are enabled the adv7170/adv7171 is config- ured in a master timing mode. mode register 2 mr2 (mr27Cmr20) (address [sr4-sr0] = 02h) mode register 2 is an 8-bit-wide register. figure 40 shows the various operations under the control of mode register 2. this r egister can be read from as well as written to. mr2 bit description square pixel mode control (mr20) this bit is used to set up square pixel mode. this is available in slave mode only. for ntsc, a 24.54 mhz clock must be sup- plied. for pal, a 29.5 mhz clock must be supplied. mr11 mr10 mr17 mr12 mr13 mr15 mr16 mr14 closed captioning field selection 0 0 no data out 0 1 odd field only 1 0 even field only 1 1 data out (both fields) mr12 mr11 dac a control 0 normal 1 power-down mr16 dac d control mr14 dac c control mr13 dac b control mr15 interlace control 0 interlaced 1 noninterlaced mr10 color bar control 0 disable 1 enable mr17 0 normal 1 power-down 0 normal 1 power-down 0 normal 1 power-down figure 39. mode register 1 mr21 mr27 mr22 mr23 mr26 mr25 mr24 mr20 chrominance control 0 enable color 1 disable color mr24 genlock selection x 0 disable genlock 0 1 enable subcarrier reset pin 1 1 enable rtc pin mr22 mr21 low power mode select 0 disable 1 enable mr26 square pixel control 0 disable 1 enable mr20 burst control 0 enable burst 1 disable burst mr25 mr27 active video line width control 0 cci r624 output 1 cci r601 output mr23 reserved figure 40. mode register 2 mr31 mr30 mr37 mr32 mr34 mr33 mr35 mr36 mr30 mr31 reserved vbi_open 0 disable 1 enable mr32 dac output switching 0 composite 1 green/luma/y mr33 dac a blue/comp/u blue/comp/u dac b red/chroma/v red/chroma/v dac c green/luma/y composite dac d chroma output select 0 disable 1 enable mr34 teletext control 0 disable 1 enable mr35 ttx bit request mode control 0 normal 1 bit request mr36 all zeros invalid control 0 disable 1 enable mr37 figure 41. mode register 3
adv7170/adv7171 C25C rev. 0 genlock control (mr22Cmr21) these bits control the genlock feature of the adv7170/adv7171. setting mr21 to a logic 1 configures the screset/rtc pin as an input. setting mr22 to logic level 0 configures the screset/rtc pin as a subcarrier reset input. therefore, the subcarrier will reset to field 0 following a high-to-low tran- sition on the screset/rtc pin. setting mr22 to logic level 1 configures the screset/rtc pin as a real-time control input. active video line control (mr23) this bit switches between two active video line durations. a zero selects itu-r bt.470 (720 pixels pal/ntsc) and a one selects itu-r/smpte analog standard for active video dura- tion (710 pixels ntsc 702 pixels pal). chrominance control (mr24) this bit enables the color information to be switched on and off the video output. burst control (mr25) this bit enables the burst information to be switched on and off the video output. low power control (mr26) this bit enables the lower power mode of the a dv7170/adv7171. this will reduce the dac current by 45%. reserved (mr27) a logical 0 must be written to this bit. mode register 3 mr3 (mr37Cmr30) (address [sr4Csr0] = 03h) mode register 3 is an 8-bit-wide register. figure 41 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr30Cmr31) this bit is read only and indicates the revision of the device. vbi pass-through control (mr32) this bit determines whether or not data in the vertical blanking interval (vbi) is output to the analog outputs or blank ed. dac switching control (mr33) this bit is used to switch the dac outputs from scart to a euroscart configuration. a complete table of all dac output configurations is shown below. chroma output select (mr34) with this active high bit it is possible to output yuv data with a composite output on the fourth dac or a chroma output on the fourth dac (0 = cvbs; 1 = chroma) teletext enable (mr35) this bit must be set to 1 to enable teletext data insertion on the ttx pin. teletext mode control (mr36) this bit enables switching of the teletext request signal from a continuous high signal (mr36 = 0) to a bit wise request sig- nal (mr36 = 1). input default color (mr37) this bit determines the default output color from the dacs for zero input pixel data (or disconnected). a logical 0 means that the color corresponding to 00000000 will be displayed. a logical 1 forces the output color to black for 00000000 pixel input video data. table ii. dac output configuration matrix mr34 mr40 mr41 mr33 dac a dac b dac c dac d simultaneous output 0000 cvbs cvbs c y 2 composite and y/c 0001y cvbs c cvbs 2 composite and y/c 0010 cvbs cvbs c y 2 composite and y/c 0011y cvbs c cvbs 2 composite and y/c 0100 cvbs b r g rgb and composite 0101gb r cvbs rgb and composite 0110 cvbs u v y yuv and composite 0111y u v cvbs yuv and composite 1000c cvbs c y 1 composite, y and 2c 1001y cvbs c c 1 composite, y and 2c 1010c cvbs c y 1 composite, y and 2c 1011y cvbs c c 1 composite, y and 2c 1100c b r g rgb and c 1101gb r c rgb and c 1110c u v y yuv and c 1111y u v c yuv and c cvbs: composite video baseband signal y: luminance component signal (for yuv or y/c mode) c: chrominance signal (for y/c mode) u: chrominance component signal (for yuv mode) v: chrominance component signal (for yuv mode) r: red component video (for rgb mode) g: green component video (for rgb mode) b: blue component video (for rgb mode) note each dac can be powered on or off individually with the following control bits (0 = on, 1 = off). mr13-dac c mr14-dac d mr15-dac b mr16-dac a
adv7170/adv7171 C26C rev. 0 mode register 4 mr4 (mr47Cmr40) (address (sr4Csr0) = 04h) mode register 4 is a 8-bit-wide register. figure 42 shows the various operations under the control of mode register 4. mr4 bit description output select (mr40) this bit specifies if the part is in composite video or rgb/yuv mode. note that in rgb/yuv mode the composite signal is still available. rgb/yuv control (mr41) this bit enables the output from the rgb dacs to be set to yuv output video standard. rgb sync (mr42) this bit is used to set up the rgb outputs with the sync infor- mation encoded on all rgb outputs. vsync _3h control (mr43) when this bit is enabled (1) in slave mode, it is possible to drive the vsync active low input for 2.5 lines in pal mode and 3 lines in ntsc mode. when this bit is enabled in mas- ter mode, the adv7170/adv7171 outputs an active low vsync signal for 3 lines in ntsc mode and 2.5 lines in pal mode. mr41 mr40 mr47 mr42 mr44 mr43 mr45 mr46 output select 0 yc output 1 rgb/yuv output mr40 rgb sync 0 disable 1 enable mr42 pedestal control 0 pedestal off 1 pedestal on mr44 sleep mode control 0 disable 1 enable mr46 active video filter control 0 enable 1 disable mr45 mr47 (0) zero should be written to this bit vsync _3h 0 disable 1 enable mr43 rgb/yuv control 0 rgb output 1 yuv output mr41 figure 42. mode register 4 pedestal control (mr44) this bit specifies whether a pedestal is to be generated on the ntsc composite video signal. this bit is invalid if the adv7170/adv7171 is configured in pal mode. active video filter switching (mr45) this bit controls the filter mode applied outside the active video portion of the line. this filter ensures that the sync rise and fall times are always on spec regardless of which luma filter is se- lected. a logic 1 enables this mode. sleep mode control (mr46) when this bit is set (1) sleep mode is enabled. with this mode enabled, the adv7170/adv7171 power consumption is reduced to typically 200 na. the i 2 c registers can be written to and read from when the adv7170/adv7171 is in sleep mode. if mr46 is set to a (0) when the device is in sleep mode, the adv7170/adv7171 will come out of sleep mode and resume normal operation. also, if the reset signal is applied during sleep mode the adv7170/adv7171 will come out of sleep mode and resume normal operation. reserved (mr47) a logical 0 should be written to this bit. timing register 0 (tr07Ctr00) (address [sr4Csr0] = 07h) figure 43 shows the various operations under the control of timing register 0. this register can be read from as well as written to. tr01 tr00 tr07 tr02 tr03 tr05 tr06 tr04 timing register reset tr07 black input control 0 enable 1 disable tr03 pixel port control 0 8 bit 1 16 bit tr06 master/slave control 0 slave timing 1 master timing tr00 luma delay 0 0 0ns delay 0 1 74ns delay 1 0 148ns delay 1 1 222ns delay tr05 tr04 timing mode selection 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 tr02 tr01 figure 43. timing register 0
adv7170/adv7171 C27C rev. 0 tr0 bit description master/slave control (tr00) this bit controls whether the adv7170/adv7171 is in master or slave mode. timing mode control (tr02Ctr01) these bits control the timing mode of the adv7170/adv7171. these modes are described in more detail in the timing and control section of the data sheet. blank control (tr03) this bit controls whether the blank input is used when the part is in slave mode. luma delay control (tr05Ctr04) these bits control the addition of a luminance delay. each bit represents a delay of 74 ns. pixel port select (tr06) this bit is used to set the pixel port to accept 8-bit or 16-bit data. if an 8-bit input is selected the data will be set up on pins p7Cp0. timing register reset (tr07) toggling tr07 from low to high and low again resets the inter- nal timing counters. this bit should be toggled after power-up, reset or changing to a new timing mode. tr11 tr10 tr17 tr12 tr13 tr15 tr16 tr14 hsync to pixel data adjustment tr17 tr16 000 3 t pclk 011 3 t pclk 102 3 t pclk 113 3 t pclk hsync to field/ vsync delay tr13 tr12 000 3 t pclk 014 3 t pclk 108 3 t pclk 1 1 16 3 t pclk t b hsync width 001 3 t pclk 014 3 t pclk 1 0 16 3 t pclk 1 1 128 3 t pclk tr11 tr10 t a hsync to field rising edge delay (mode 1 only) x0t b x1t b + 32 m s tr15 tr14 t c vsync width (mode 2 only) tr15 tr14 001 3 t pclk 014 3 t pclk 1 0 16 3 t pclk 1 1 128 3 t pclk line 313 line 314 line 1 t b timing mode 1 (master/pal) hsync field/ vsync t a t c figure 44. timing register 1 timing register 1 (tr17Ctr10) (address (sr4Csr0) = 08h) timing register 1 is a 8-bit-wide register. figure 44 shows the various operations under the control of timing register 1. this register can be read from as well writ- ten to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync width (tr11Ctr10) these bits adjust the hsync pulsewidth. hsync to vsync /field delay control (tr13Ctr12) these bits adjust the position of the hsync output relative to the field/ vsync output. hsync to field delay control (tr15Ctr14) when the adv7170/adv7171 is in timing mode 1, these bits adjust the position of the hsync output relative to the field output rising edge. vsync width (tr15Ctr14) when the adv7170/adv7171 is configured in timing mode 2, these bits adjust the vsync pulsewidth. hsync to pixel data adjust (tr17Ctr16) this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. this adjustment is available in both master and slave timing modes.
adv7170/adv7171 C28C rev. 0 subcarrier frequency register 3C0 (fsc3Cfsc0) (address [sr4Csr0] = 09hC02h) these 8-bit-wide registers are used to set up the subcarrier frequency. the value of these registers is calculated by using the following equation: subcarrier frequency register = 2 32 1 f clk f scf i.e.: ntsc mode, f clk = 27 mhz, f scf = 3.5795454 mhz subcarrier frequency value = 2 32 1 27 10 6 3.5795454 10 6 = 21f07c16 hex figure 45 shows how the frequency is set up by the four registers. subcarrier phase register (fp7Cfp0) (address [sr4Csr0] = 0dh) this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41 . for normal operation this register is set to 00hex. subcarrier frequency reg 3 subcarrier frequency reg 2 subcarrier frequency reg 1 subcarrier frequency reg 0 fsc30 fsc29 fsc27 fsc25 fsc28 fsc24 fsc31 fsc26 fsc22 fsc21 fsc19 fsc17 fsc20 fsc16 fsc23 fsc18 fsc14 fsc13 fsc11 fsc9 fsc12 fsc8 fsc15 fsc10 fsc6 fsc5 fsc3 fsc1 fsc4 fsc0 fsc7 fsc2 figure 45. subcarrier frequency register closed captioning even field data register 1C0 (ced15Cced00) (address [sr4Csr0] = 0eC0fh) these 8- bit-wide registers are used to set up the closed captioning exte nded data bytes on even fields. figure 46 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ced6 ced5 ced3 ced1 ced4 ced2 ced0 ced7 ced14 ced13 ced11 ced9 ced12 ced10 ced8 ced15 figure 46. closed captioning extended data register closed captioning odd field data register 1C0 (ccd15Cccd00) (subaddress [sr4Csr0] = 10C11h) these 8-bit-wide registers are used to set up the closed captio ning data bytes on odd fields. figure 47 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ccd6 ccd5 ccd3 ccd1 ccd4 ccd2 ccd0 ccd7 ccd14 ccd13 ccd11 ccd9 ccd12 ccd10 ccd8 ccd15 figure 47. closed captioning data register ntsc pedestal/pal teletext control registers 3C0 (pce15C0, pco15C0)/(txe15C0, txo15C0) (subaddress [sr4Csr0] = 12C15h) these 8-bit-wide registers are used to enable the ntsc pedes- tal/pal teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. figures 48 and 49 show the four control registers. a logic 1 in any of the bits of these registers has the effect of turning the pedestal off on the equivalent line when used in ntsc. a logic 1 in any of the bits of these registers has the effect of turning teletext on on the equivalent line when used in pal. field 1/3 pco6 pco5 pco3 pco1 pco4 pco2 pco0 pco7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pco14 pco13 pco11 pco9 pco12 pco10 pco8 pco15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 1/3 field 2/4 pce6 pce5 pce3 pce1 pce4 pce2 pce0 pce7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pce14 pce13 pce11 pce9 pce12 pce10 pce8 pce15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 2/4 figure 48. pedestal control registers field 1/3 field 1/3 field 2/4 field 2/4 txo6 txo5 txo3 txo1 txo4 txo2 txo0 txo7 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txo14 txo13 txo11 txo9 txo12 txo10 txo8 txo15 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txe6 txe5 txe3 txe1 txe4 txe2 txe0 txe7 txe14 txe13 txe11 txe9 txe12 txe10 txe8 txe15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 figure 49. teletext control registers teletext control register tc07 (tc07Ctc00) (address [sr4Csr0] = 19h) teletext control register is an 8-bit-wide register. see figure 50. ttxreq rising edge control (tc07Ctc04) these bits control the position of the rising edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. see figure 59. ttxreq falling edge control (tc03Ctc00) these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. this controls the active window for teletext data. increasing this value reduces the amount of teletext bits below the default of 360. if bits tc03-tc00 are 00hex when bits tc07Ctc04 are changed, the falling edge of ttreq will track that of the rising edge (i.e., the time between the falling and rising edge remains constant). see figure 59. cgms_wss register 0 c/w0 (c/w07Cc/w00) (address [sr4Csr0] = 16h) cgms_wss register 0 is an 8-bit-wide register. figure 51 shows the operations under the control of this register.
adv7170/adv7171 C29C rev. 0 tc01 tc00 tc07 tc02 tc04 tc03 tc05 tc06 ttxreq rising edge control tc07 tc06 tc05 tc04 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk ttxreq falling edge control tc03 tc02 tc01 tc00 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk figure 50. teletext control register cgms crc check control 0 disable 1 enable c/w04 wide screen signal control 0 disable 1 enable c/w07 c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 cgms odd field control 0 disable 1 enable c/w05 c/w03Cc/w00 cgms data bits cgms even field control 0 disable 1 enable c/w06 figure 51. cgms_wss register 0 c/w0 bit description cgms data bits (c/w03Cc/w00) these four data bits are the final four bits of cgms data output stream. note it is cgms data only in these bit positions, i.e., wss data does not share this location. cgms crc check control (c/w04) when this bit is enabled (1), the last six bits of the cgms data, i.e., the crc check sequence, is calculated internally by the adv7170/adv7171. if this bit is disabled (0) the crc values in the register are output to the cgms data stream. cgms odd field control (c/w05) when this bit is set (1), cgms is enabled for odd fields. note this is only valid in ntsc mode. cgms even field control (c/w06) when this bit is set (1), cgms is enabled for even fields. note this is only valid in ntsc mode. wss control (c/w07) when this bit is set (1), wide screen signaling is enabled. note this is only valid in pal mode. cgms_wss register 1 c/w1 (c/w17Cc/w10) (address [sr4Csr0] = 17h) cgms_wss register 1 is an 8-bit-wide register. figure 52 shows the operations under the control of this register. c/w1 bit description cgms/wss data bits (c/w15Cc/w10) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. cgms data bits (c/w17Cc/w16) these bits are cgms data bits only. cgms_wss register 2 c/w1 (c/w27Cc/w20) (address [sr4Csr0] = 18h) cgms_wss register 2 is an 8-bit-wide register. figure 53 shows the operations under the control of this register. c/w2 bit description cgms/wss data bits (c/w27Cc/w20) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15Cc/w10 cgms/wss data c/w17 c/w16 cgms data only figure 52. cgms_wss register 1 c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 c/w27Cc/w20 cgms/wss data figure 53. cgms_wss register 2
adv7170/adv7171 C30C rev. 0 the adv7170/adv7171 is a highly integrated circuit containing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. figure 54, recommended analog circuit layout, shows the analog interface between the device and monitor. the layout should be optimized for lowest no ise on the adv7170/ adv7171 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should by minimized to minimize induc- tive ringing. ground planes the ground plane should encompass all adv7170/adv7171 ground pins, voltage reference circuitry, power supply bypass circuitry for the adv7170/adv7171, the analog output traces, and all the digital signal traces lea ding up to the adv7170/ adv7171. the ground plane is the boards common ground plane. this should be as substantial as possible to maximize heat spreading and power dissipation on the board. power planes the adv7170/adv7171 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the adv7170/adv7171. the metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7170/adv7171 power pins and voltage refer- ence circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. appendix 1 board design and layout considerations supply decoupling for optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is obtained with 0.1 m f ceramic capacitor decoupling. each group of v aa pins on the adv7170/adv7171 must have at least one 0.1 m f decoupling capacitor to gnd. these capacitors should be placed as close to the device as possible. it is important to note that while the adv7170/adv7171 con- tains circuitry to reject power supply noise, this rejection de- creases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the adv7170/adv7171 should be iso- lated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the adv7170/adv7171 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not the analog power plane. analog signal interconnect the adv7170/adv7171 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 75 w load resistor connected to gnd. these resistors should be placed as close as possible to the adv7170/adv7171 to minimize reflections. the adv7170/adv7171 should have no inputs left floating. any inputs that are not required should be tied to ground.
adv7170/adv7171 C31C rev. 0 75 v 27 26 s video 31 32 5k v +5v (v cc ) 150 v 24 5k v +5v (v cc ) mpu bus 44 22 15 17 16 10, 19, 21 29, 43 18 23 34 38C42, 2C9, 12C14 1, 11, 20, 28, 30 0.1 m f 0.01 m f 0.1 m f +5v (v aa ) 0.1 m f +5v (v aa ) 10k v +5v (v aa ) 27mhz clock (same clock as used by mpeg2 decoder) power supply decoupling for each power supply group 10 m f 33 m f gnd l1 (ferrite bead) +5v 25 33 gnd alsb hsync field/ vsync blank reset clock r set sdata sclock dac b dac c dac d v aa v ref comp p15Cp0 +5v (v aa ) 75 v 75 v 75 v 35 screset/rtc adv7170/ adv7171 unused inputs should be grounded dac a 100 v 100 v 4k v +5v (v aa ) 100nf reset 37 ttx 36 ttxreq (v cc ) 100k v 100k v +5v (v aa ) ttx ttxreq teletext pull-up and pull-down resistors should only be used if these pins are not connected figure 54. recommended analog circuit layout the circuit below can be used to generate a 13.5 mhz waveform using the 27 mhz clock and the hsync pulse. this waveform is guaranteed to produce the 13.5 mhz clock in synchronization with the 27 mhz clock. this 13.5 mhz clock can be used if 13.5 mhz clock is required by the mpeg decoder. this will guarantee that the cr and cb pixel information is input to the adv7170/adv7171 in the correct sequence. d q ck d q ck clock hsync 13.5mhz figure 55. circuit to generate 13.5 mhz
adv7170/adv7171 C32C rev. 0 the adv7170/adv7171 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. after the clock run-in signal, the blanking level is held for two d ata bits and is followed by a logic level 1 start bit. 16 b its of data follow the start bit. these consist of two 8-bit bytes, seven data bits and one odd parity bit. the data for these bytes is stored in closed captioning data registers 0 and 1. the adv7170/adv7171 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. all clock run-in signals and timing to support closed capt ion- ing on lines 21 and 284 are automatically generated by the adv7170/adv7171. all pixels inputs are ignored during lines 21 and 284. appendix 2 closed captioning 12.91 m s s t a r t p a r i t y p a r i t y d0Cd6 d0Cd6 10.003 m s 33.764 m s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 6 0.25 m s two 7-bit + parity ascii characters (data) 27.382 m s byte 0 byte 1 figure 56. closed captioning waveform (ntsc) fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the adv7170/adv7171 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. the data must be loaded at least one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical imple- mentation of this method is to use vsync to interrupt a micro- processor, which will in turn load the new data (two bytes) every field. if no new data is required for transmission, you must insert zeros in both the data registers; this is called nulling. it is also important to load control codes, all of which are double bytes, on line 21, or a tv will not recognize them. if you have a message like hello world, which has an odd num- ber of characters, it is important to pad it out to an even number to get end of caption 2-byte control code to land in the same field.
adv7170/adv7171 C33C rev. 0 the adv7170/adv7171 supports copy generation management system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can only be transmitted when the adv7170/adv7171 is configured in ntsc mode. the cgms data is 20 bits long, the function of each of these bits is as shown below. the cgms data is preceded by a refer - ence pulse of the same amplitude and duration as a cgms bit (see figure 57). the bits are output from the configuration registe rs in the following order; c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/w11 = c9, c/w12 = c10, c/w13 = c11, c/w14 = c12, c/w15 = c13, c/w16 = c14, c/w17 = c15, c/w20 = c0, c/w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w25 = c5, c/w26 = c6, c/w27 = c7. if the bit c/w04 is set to a logic 1, the last six bits, c19Cc14, which comprise the 6-bit crc check sequence, are calcul ated automatically on the adv7170/adv7171 based on the lower 14 bits (c0C c13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if c/w04 is set to a logic 0, all 20 bits (c0Cc19) are directly output from the cgms registers (no crc calculated, must be calculated by the user) . function of cgms bits word 0 C 6 bits word 1 C 4 bits word 2 C 6 bits crc C 6 bits crc polynomial = x 6 + x + 1 (preset to 111111) word 0 1 0 b1 aspect ratio 16:94:3 b2 display format letterbox normal b3 undefined word 0 b4, b5, b6 identification information about video and other signals (e.g., audio) word 1 b7, b8, b9, b10 identification signal incidental to word 0 word 2 b11, b12, b13, b14 identification signal and information incidental to word 0 crc sequence 49.1 m s 6 0.5 m s 11.2 m s 2.235 m s 6 20 m s ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 100 ire 70 ire 0 ire C40 ire figure 57. cgms waveform diagram appendix 3 copy generation management system (cgms)
adv7170/adv7171 C34C rev. 0 appendix 4 wide screen signaling the adv7170/adv7171 supports wide screen signalling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the adv7170/adv7171 is configured in pal mode. the wss data is 14 bits long, the function of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code (see figure 58 ). the bits are output from the configuration registers in the following order; c/w20 = w0, c/w21 = w1, c/ w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if the bit c/w07 is set to a logic 1 it enables the wss data to transmitted on line 23. the latter portion of li ne 23 (42.5 m s from the falling edge of hsync ) is available for the insertion of video. function of cgms bits bit 0Cbit 2 aspect ratio/format/position bit 3 is odd parity check of bit 0Cbit 2 b0 b1 b2 b3 aspect ratio format position 0001 4:3 full format nonapplicable 1000 14:9 letterbox center 0100 14:9 letterbox top 1101 16:9 letterbox center 0010 16:9 letterbox top 1011 >16:9 letterbox center 0111 14:9 full format center 1110 16:9 nonapplicable nonapplicable 11.0 m s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 38.4 m s 42.5 m s figure 58. wss waveform diagram b4 0 camera mode 1 film mode b5 0 standard coding 1 motion adaptive color plus b6 0 no helper 1 modulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0 no surround sound information 1 surround sound mode b12 reserved b13 reserved
adv7170/adv7171 C35C rev. 0 appendix 5 teletext insertion t pd is the time needed by the adv7170/adv7171 to interpolate input data on ttx and insert it onto the cvbs or y outputs, such that it appears t syntxtout = 10.2 m s after the leading edge of the horizontal signal. time txt del is the pipeline delay time by the source that is gated by the ttreq signal in order to deliver ttx data. with the programmability offered with ttxreq signal on the rising/falling edges, the ttx data is always inserted at the correct position of 10.2 m s after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipeline delays. the width of the ttxreq signal must always be maintained to allow the insertion of 360 (to comply with the teletext standard pal-wst) teletext bits at a text data rate of 6.9375 mbits/s, this is achieved by setting tc03Ctc00 to zero. the insertion wi n- dow is not open if the teletex enable bit (mr34) is set to zero. teletext protocol the relationship between the ttx bit clock (6.9375 mhz) and the system clock (27 mhz) for 50 hz is given as follows: (27 mhz/4) = 6.75 mhz (6.9375 10 6 /6.75 10 6 ) = 1.027777 thus 37 ttx bits correspond to 144 clocks (27 mhz) and each bit has a width of almost four clock cycles. the adv7170/adv7171 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal that can be outputted on the cvbs and y outputs. at the ttx input the bit duration scheme repeats after every 37 ttx bits or 144 clock cycles. the protocol requires that ttx bi ts 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. after 37 ttx bits, the next bits with th ree clock cycles are 47, 56, 65 and 74. this scheme holds for all following cycles of 37 ttx bits, until all 360 ttx bits are completed. all teletext lines are implemented in the say way. individual control of teletext lines is controlled by teletext setup registers. address & data run-in clock teletext vbi line 45 bytes (360 bits) C pal figure 59. teletext vbi line programmable pulse edges t syntxtout t pd t pd 10.2 m s txt st txt del cvbs/y hsync txtreq txt data t syntxtout = 10.2 m s t pd = pipeline delay through adv7170/adv7171 txt del = ttxreq to ttx (programmable range = 4 bits [0C15 clock cycles]) figure 60. teletext functionality diagram
adv7170/adv7171 C36C rev. 0 appendix 6 ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire C40 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 61. ntsc composite video levels 100 ire 7.5 ire 0 ire C40 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 62. ntsc luma video levels 650mv 232.2mv 1067.7mv 0mv peak chroma blank/black level 286mv (pk-pk) 835mv (pk-pk) peak chroma figure 63. ntsc chroma video levels 100 ire 7.5 ire 0 ire C40 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv figure 64. ntsc rgb video levels
adv7170/adv7171 C37C rev. 0 ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire C40 ire peak composite ref white sync level blank/black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv figure 65. ntsc composite video levels 100 ire 0 ire C40 ire ref white sync level blank/black level 714.2mv 1052.2mv 338mv 52.1mv figure 66. ntsc luma video levels 650mv 198.4mv 1101.6mv 0mv peak chroma blank/black level 307mv (pk-pk) peak chroma 903.2mv (pk-pk) figure 67. ntsc chroma video levels 100 ire 0 ire C40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv figure 68. ntsc rgb video levels
adv7170/adv7171 C38C rev. 0 pal waveforms 1284.2mv 1047.1mv 350.7mv 50.8mv peak composite ref white sync level blank/black level 696.4mv figure 69. pal composite video levels 1047mv 350.7mv 50.8mv ref white sync level blank/black level 696.4mv figure 70. pal luma video levels 650mv 207.5mv 1092.5mv 0mv peak chroma blank/black level 300mv (pk-pk) 885mv (pk-pk) peak chroma figure 71. pal chroma video levels 1050.2mv 351.8mv 51mv ref white sync level blank/black level 698.4mv figure 72. pal rgb video levels
adv7170/adv7171 C39C rev. 0 betacam level 0mv 171mv 334mv 505mv 0mv 2 171mv 2 334mv 2 505mv white yellow cyan green magenta red blue black figure 73. ntsc 100% color bars, no pedestal u levels betacam level 0mv 158mv 309mv 467mv 0mv C158mv C309mv C467mv white yellow cyan green magenta red blue black figure 74. ntsc 100% color bars with pedestal u levels smpte level 0mv 118mv 232mv 350mv 0mv C118mv C232mv C350mv white yellow cyan green magenta red blue black figure 75. pal 100% color bars, u levels uv waveforms betacam level 0mv 82mv 423mv 505mv 0mv C82mv C505mv C423mv white yellow cyan green magenta red blue black figure 76. ntsc 100% color bars, no pedestal v levels betacam level 0mv 76mv 391mv 467mv 0mv C76mv C467mv C391mv white yellow cyan green magenta red blue black figure 77. ntsc 100% color bars with pedestal v levels smpte level 0mv 57mv 293mv 350mv 0mv C57mv C350mv C293mv white yellow cyan green magenta red blue black figure 78. pal 100% color bars, v levels
adv7170/adv7171 C40C rev. 0 if an output filter is required for the cvbs, y, uv, chroma and rgb outputs of the adv7170/adv7171, the filter shown in figure 79 can be used. plots of the filter characteristics are shown in figure 80, figure 81 and figure 82. an output filter appendix 7 optional output filter l 1 m h l 2.7 m h l 0.68 m h r 75 v r 75 v c 470pf c 330pf c 56pf in out figure 79. output filter frequency C hz 10k 100m 100k 1m 10m decibels 0 C5 C70 C10 C15 C20 C25 C30 C35 C40 C45 C50 C55 C60 C65 v db C op figure 80. output filter plot is not required if the outputs of the adv7170/adv7171 are connected to most analog monitors or analog tvs, however if the output signals are applied to a system where sampling is used (e.g., digital tvs), then a filter is required to prevent aliasing. frequency C mhz 1 100 decibels 10 0 C35 C5 C10 C15 C20 C25 C30 v db C op figure 81. output filter plot close-up frequency C mhz 110 decibels 2 0.0 C3.5 C0.5 C1.0 C1.5 C2.0 C2.5 C3.0 v db C op 468 C4.5 C4.0 3 579 filter 82. output filter plot close-up
adv7170/adv7171 C41C rev. 0 appendix 8 optional dac buffering when external buffering is needed of the adv7170/adv7171 dac outputs, the configuration in figure 83 is recommended. this configuration shows the dac outputs running at half (18 ma) their full current (36 ma) capability. this will allow the adv7170/adv7171 to dissipate less power; the analog cur- rent is reduced by 50% with a r set of 300 w and a r load of 75 w . this mode is recom mended for 3.3 v operation as optimum performance is obtained from the dac outputs at 18 ma with a v aa of 3.3 v. this buffer also adds extra isolation on the video outputs (see buffer circuit in figure 84). when calculating absolute output full-scale current and voltage, use the following equations: v out = i out r load i out = v ref k () r set k = 4.2146 constant , v ref = 1.235 v adv7170/adv7171 v ref digital core pixel port 300 v r set v aa output buffer dac a output buffer output buffer output buffer dac c dac d dac b cvbs luma chroma cvbs figure 83. output dac buffering configuration 2n2907 75 v 75 v output to tv/monitor 36 v input v aa figure 84. recommended output dac buffer
adv7170/adv7171 C42C rev. 0 appendix 9 recommended register values the adv7170/adv7171 registers can be set depending on the user standard required. the following examples give the various register formats for several video standards. in each case the output is set to composite o/p with all dacs powered up and with the blank input control disabled. addi- tionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. in the examples shown, the timing mode is set to mode 0 in slave format. tr02Ctr00 of the timing register 0 control the tim- ing modes. for a detailed explanation of each bit in the com- mand registers, please turn to the register programming section of the data sheet. tr07 should be toggled after setting up a new timing mode. timing register 1 provides additional control over the position and duration of the timing signals. in the examples, this register is programmed in default mode. pal b, d, g, h, i (f sc = 4.43361875 mhz) address data 00hex mode register 0 05hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss reg 0 00hex 17hex cgms_wss reg 1 00hex 18hex cgms_wss reg 2 00hex 19hex teletext control register 00hex pal m (f sc = 3.57561149 mhz) address data 00hex mode register 0 02hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 a3hex 0ahex subcarrier frequency register 1 efhex 0bhex subcarrier frequency register 2 e6hex 0chex subcarrier frequency register 3 21hex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss reg 0 00hex 17hex cgms_wss reg 1 00hex 18hex cgms_wss reg 2 00hex 19hex teletext control register 00hex pal n (f sc = 4.43361875 mhz) address data 00hex mode register 0 05hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss reg 0 00hex 17hex cgms_wss reg 1 00hex 18hex cgms_wss reg 2 00hex 19hex teletext control register 00hex pal-60 (f sc = 4.43361875 mhz) address data 00hex mode register 0 04hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex
adv7170/adv7171 C43C rev. 0 pal-60 (continued) (f sc = 4.43361875 mhz) address data 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss reg 0 00hex 17hex cgms_wss reg 1 00hex 18hex cgms_wss reg 2 00hex 19hex teletext control register 00hex power-up reset values ntsc (f sc = 3.5795454 mhz) address data 00hex mode register 0 00hex 01hex mode register 1 58hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 10hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 16hex 0ahex subcarrier frequency register 1 7chex 0bhex subcarrier frequency register 2 f0hex 0chex subcarrier frequency register 3 21hex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss reg 0 00hex 17hex cgms_wss reg 1 00hex 18hex cgms_wss reg 2 00hex 19hex teletext control register 00hex
adv7170/adv7171 C44C rev. 0 appendix 10 output waveforms 0.6 0.4 0.2 0.0 2 0.2 l608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 microseconds noise reduction: 0.00 db apl = 39.1% precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 m s frames selected: 1 2 3 4 volts figure 85. 100%/75% pal color bars microseconds apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 m s frames selected: 1 0.5 0.0 l575 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 volts figure 86. 100%/75% pal color bars luminance
adv7170/adv7171 C45C rev. 0 apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 m s frames selected: 1 0.5 0.0 C0.5 10.0 30.0 40.0 50.0 60.0 20.0 microseconds l575 volts no bruch signal figure 87. 100%/75% pal color bars chrominance apl = 44.6% precision mode off 525 line ntsc no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 m s frames selected: 1 2 microseconds 0.5 0.0 C50.0 50.0 100.0 ire:flt volts f1 l76 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.0 figure 88. 100%/75% ntsc color bars
adv7170/adv7171 C46C rev. 0 noise reduction: 15.05db apl = 44.7% precision mode off 525 line ntsc no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 m s frames selected: 1 2 microseconds 10.0 20.0 30.0 40.0 50.0 60.0 0.6 0.4 0.2 0.0 C0.2 50.0 0.0 ire:flt volts f2 l238 figure 89. 100%/75% ntsc color bars luminance noise reduction: 15.05db apl needs sync = source! precision mode off 525 line ntsc no filtering synchronous sync = b slow clamp to 0.00 v at 6.72 m s frames selected: 1 2 microseconds 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.4 0.2 0.0 C0.2 C0.4 volts 50.0 C50.0 f1 l76 ire:flt figure 90. 100%/75% ntsc color bars chrominance
adv7170/adv7171 C47C rev. 0 apl = 39.6% sound in sync off v u yi yl g r m g cy m g cy g r 75% 100% b b system line l608 angle (deg) 0.0 gain x 1.000 0.000db 625 line pal burst from source display +v & Cv figure 91. pal vector plot apl = 45.1% setup 7.5% r-y b-y yi g cy m g cy i r 75% 100% b b system line l76f1 angle (deg) 0.0 gain x 1.000 0.000db 525 line ntsc burst from source q Cq Ci figure 92. ntsc vector plot
adv7170/adv7171 C48C rev. 0 color bar (ntsc) wfm --> fcc color bar field = 2 line = 28 luminance level (ire) 0.4 0.2 0.2 0.0 0.2 0.1 0.2 0.1 0.0 C0.2 C0.2 C0.3 C0.2 C0.3 0.0 0.0 . . . . . C0.1 C0.2 C0.2 C0.1 C0.3 C0.2 - - - - - chrominance level (ire) chrominance phase (deg) gray yellow cyan green magenta red blue black average: 32 --> 32 reference 75/7.5/75/7.5 color bar standard 30.0 20.0 10.0 0.0 C10.0 1.0 0.0 C1.0 0.0 C1.0 C2.0 figure 93. ntsc color bar measurement dgdp (ntsc) wfm --> mod 5 step block mode start f2 l64, step = 32, end = 192 differential gain (%) min = 0.00 max = 0.11 p-p/max = 0.11 0.00 0.08 0.07 0.11 0.07 0.05 0.3 0.2 0.1 0.0 C0.1 0.20 0.15 0.10 0.05 C0.00 C0.05 C0.10 0.00 0.03 C0.02 0.14 0.10 0.10 differential phase (deg) min = C0.02 max = 0.14 pk-pk = 0.16 1st 2nd 3rd 4th 5th 6th figure 94. ntsc differential gain and phase measurement
adv7170/adv7171 C49C rev. 0 luminance nonlinearity (ntsc) wfm --> 5 step field = 2 line = 21 luminance nonlinearity (%) pk-pk = 0.2 99.9 100.0 99.9 99.9 99.8 100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 99.3 99.2 99.1 99.0 98.9 98.8 98.7 98.6 1st 2nd 3rd 4th 5th figure 95. ntsc luminance nonlinearity measurement chrominance am pm (ntsc) wfm --> appropriate full field (both fields) bandwidth 100hz to 500khz C75.0 am noise C68.4db rms C70.0 C65.0 C60.0 C55.0 C50.0 C45.0 C40.0 db rms C75.0 pm noise C64.4db rms C70.0 C65.0 C60.0 C55.0 C50.0 C45.0 C40.0 db rms (0db = 714mv p-p with agc for 100% chrominance level) figure 96. ntsc ampm noise measurement
adv7170/adv7171 C50C rev. 0 noise spectrum (ntsc) wfm --> pedestal field = 2 line = 64 amplitude (0 db = 714mv p-p) noise level = C80.1 db rms bandwidth 100khz to full C5.0 C10.0 C15.0 C20.0 C25.0 C30.0 C35.0 C40.0 C45.0 C50.0 C55.0 C60.0 C65.0 C70.0 C75.0 C80.0 C85.0 C90.0 C95.0 C100.0 1.0 2.0 3.0 4.0 5.0 6.0 mhz figure 97. ntsc snr pedestal measurement noise spectrum (ntsc) wfm --> ramp signal field = 2 line = 64 amplitude (0 db = 714mv p-p) noise level = C61.7 db rms bandwidth 10khz to full (tilt null) C5.0 C10.0 C15.0 C20.0 C25.0 C30.0 C35.0 C40.0 C45.0 C50.0 C55.0 C60.0 C65.0 C70.0 C75.0 C80.0 C85.0 C90.0 C95.0 C100.0 1.0 2.0 3.0 4.0 5.0 mhz figure 98. ntsc snr ramp measurement
adv7170/adv7171 C51C rev. 0 parade smpte/ebu pal mv y(a) mv pb(b) mv pr(c) 700 600 500 400 300 200 100 0 2 100 2 200 2 300 250 200 150 100 50 C50 C100 C150 C200 C250 0 250 200 150 100 50 C50 C100 C150 C200 C250 0 figure 99. pal yuv parade plot lightning colorbars: 75% smpte/ebu (50hz) average 32 --> 32 l183 pk-white (100%) 700.0mv setup 0.0% color pk-pk 525.0mv yi C274.82 0.93% g C173.24 0.19% r C88.36 0.19% cy 88.31 0.28% m 174.35 C0.65% b 260.51 C0.14% yi 462.80 C0.50% g 307.54 C0.21% r 156.63 C0.22% b-y w yi g r b g cy r-y w yi m r cy C262.17 C0.13% g C218.70 C0.51% b C42.54 0.69% yi 41.32 C0.76% m 212.28 C3.43% r 252.74 C3.72% cy 864.78 C0.88% m 216.12 C0.33% b 61.00 1.92% cy m b color pk-pk: b-y 532.33mv 1.40% r-y 514.90mv C1.92% pk-white: 700.4mv (100%) setup C0.01% delay: b-y C6ns r-y C6ns figure 100. pal yuv lighting plot
adv7170/adv7171 C52C rev. 0 component noise line = 202 amplitude (0db = 700mv p-p) noise db rms bandwidth 10khz to 5.0mhz C5.0 C10.0 C15.0 C20.0 C25.0 C30.0 C35.0 C40.0 C45.0 C50.0 C55.0 C60.0 C65.0 C70.0 C75.0 C80.0 C85.0 C90.0 C95.0 C100.0 1.0 2.0 3.0 4.0 5.0 mhz 6.0 0.0 -->y C82.1 pb C82.3 pr C83.3 figure 101. pal yuv snr plot component multiburst line = 202 amplitude (0db = 100% of 688.1mv 683.4mv 668.9mv 0.04 C0.02 C0.05 C0.68 C2.58 C8.05 (db) 0.49 0.99 2.00 3.99 4.79 5.79 0.49 0.99 1.99 2.39 2.89 0.49 0.99 1.99 2.39 2.89 0.0 C5.0 C10.0 y 0.0 C5.0 C10.0 pb 0.0 C5.0 C10.0 pr mhz 0.21 0.23 C0.78 C2.59 C7.15 0.25 0.25 C0.77 C2.59 C7.13 figure 102. pal yuv multiburst response
adv7170/adv7171 C53C rev. 0 r m g yi bk b g cy component vector smpte/ebu, 75% figure 103. pal yuv vector plot mv green (a) mv blue (b) mv red (c) 700 600 500 400 300 200 100 0 2 100 2 200 2 300 700 600 500 400 300 200 100 0 700 600 500 400 300 200 100 0 2 100 2 200 2 300 2 100 2 200 2 300 figure 104. pal rgb waveforms
adv7170/adv7171 C54C rev. 0 index contents page no. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . 1 adv7170/adv7171 specifications . . . . . . . . . . . . . 2 dynamic specifications . . . . . . . . . . . . . . . . . . . . 4 timing specifications . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . 8 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin function descriptions . . . . . . . . . . . . . . . . . 9 general description . . . . . . . . . . . . . . . . . . . . . . . . 10 data path description . . . . . . . . . . . . . . . . . . . . . 10 internal filter response . . . . . . . . . . . . . . . . . . . 10 color bar generation . . . . . . . . . . . . . . . . . . . . . . 13 square pixel mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13 color signal control . . . . . . . . . . . . . . . . . . . . . . 13 burst signal control . . . . . . . . . . . . . . . . . . . . . . 13 ntsc pedestal control . . . . . . . . . . . . . . . . . . . . . 13 pixel timing description . . . . . . . . . . . . . . . . . . . 13 subcarrier reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 real-time control . . . . . . . . . . . . . . . . . . . . . . . . . . 13 video timing description . . . . . . . . . . . . . . . . . . . 13 output video timing . . . . . . . . . . . . . . . . . . . . . . . . 21 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 mpu port description . . . . . . . . . . . . . . . . . . . . . . . 21 register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 register programming . . . . . . . . . . . . . . . . . . . . . 22 mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mode register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mode register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 timing register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 timing register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 subcarrier frequency register 3C0 . . . . . . . . 28 subcarrier phase register . . . . . . . . . . . . . . . . . . 28 closed captioning even field . . . . . . . . . . . . . . 28 closed captioning odd field . . . . . . . . . . . . . . 28 ntsc pedestal/pal teletext control registers 3C0 . . . . . . . . . . . . . . . . . . . . . 28 teletext control register tc07 . . . . . . . . . . . 28 appendix 1. board design and layout considerations . . . . . . . . . . . . . . . . . . . 30 appendix 2. closed captioning . . . . . . . . . . . . . 32 appendix 3. copy generation management systems (cgms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 appendix 4. wide screen signaling . . . . . . . . . 34 appendix 5. teletext insertion . . . . . . . . . . . . 35 appendix 6. ntsc waveforms (with pedestal) . . . . . . . . . 36 ntsc waveforms (without pedestal) . . . . . 37 pal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 uv waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 appendix 7. optional output filter . . . . . . . . 40 appendix 8. optional dac buffering . . . . . . . 41 appendix 9. recommended register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 appendix 10. output waveforms . . . . . . . . . . . . 44 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 55
adv7170/adv7171 C55C rev. 0 44-lead plastic quad flatpack (pqfp) (s-44) 0.548 (13.925) 0.546 (13.875) top view (pins down) 1 33 34 44 11 12 23 22 0.033 (0.84) 0.029 (0.74) 0.398 (10.11) 0.390 (9.91) 0.016 (0.41) 0.012 (0.30) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) seating plane 0.096 (2.44) max 0.037 (0.94) 0.025 (0.64) 8 8 0.8 8 44-lead thin plastic quad flatpack (tqfp) (su-44) top view (pins down) 1 33 34 44 11 12 23 22 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) bsc 0.394 (10.0) sq 0.472 (12.00) sq 0.041 (1.05) 0.037 (0.95) seating plane 0.047 (1.20) max 0.006 (0.15) 0.002 (0.05) outline dimensions dimensions shown in inches and (mm). c3317C8C4/98 printed in u.s.a.

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